Technical Field
The present disclosure relates to deep trench capacitors, and more specifically, to a deep trench capacitor with a lower portion that is wider than a width of the rest of the deep trench, and a compressive stress layer in the lower portion and/or a silicide outer electrode.
Related Art
Deep trench capacitors are used widely in integrated circuit chips to provide embedded dynamic random access memory (eDRAM). Information or data is stored in the memory cell in the form of charge accumulated on the capacitor. Because capacitors leak charge (generally, a capacitor is only useful for temporarily storing an electrical charge), the information (data) eventually fades unless the capacitor charge is refreshed (read, and re-written) periodically, such as every 256 microseconds. A deep trench “DT” capacitor generally comprises a first conductive electrode called the “buried plate” which is a heavily doped region of the substrate surrounding the deep trench, a thin layer of insulating material such as an oxide lining the deep trench, and a second conductive electrode such as a heavily doped polycrystalline plug (or “node”) disposed within the deep trench. The transistor may also include a field effect transistor (FET) having one of its source/drain (S/D) terminals connected to (or an extension of) the second electrode (node) of the capacitor.
FIG. 1 illustrates a DRAM cell 100 of the prior art, and generally comprising an access transistor and an associated cell capacitor. The DRAM cell is generally formed (created), as follows. Beginning with a semiconductor substrate 102, a deep trench (DT) 110 is formed, extending into substrate 102, from a top (as viewed) surface thereof. Substrate 102 may comprise a semiconductor-on-insulator (SOI) substrate having a layer 106 of silicon (SOI) on top of an insulating layer 104 which is atop the underlying silicon substrate 102. However, a bulk substrate may also be employed. Insulating layer 104 typically comprises buried oxide (BOX). Deep trench (DT) 110 is used for forming the cell capacitor (or “DT capacitor”). At current technology nodes, the deep trench 110 may have a width of about 50 nm to 200 nm and a depth of 1000 nm to 10000 nm, by way of example.
The cell capacitor generally comprises a first conductor or electrode called the “buried plate” which is a heavily doped region 112 of the substrate surrounding deep trench 110, a thin layer 114 of an insulating material lining deep trench 110, and a second conductor or electrode 116 such as a heavily doped polycrystalline plug (or “node”, “DT poly”) disposed within deep trench 110.
A cell transistor (“access transistor”) 120 may comprise a FET having one of its source/drain (S/D) terminals connected to (or an extension of) the second conductor (node) of the capacitor. FET 120 may comprise two spaced-apart diffusions 122, 124, within the surface of the substrate 102—one of which will serve as the “source” (S) and the other of which will serve as the “drain” (D) of transistor 120. A space between the two diffusion areas is called the “channel” (and is approximately where the legend “SOI” appears). A thin dielectric layer 126 is disposed on the substrate above the channel, and a “gate” structure (G) 128 is disposed over the dielectric layer 126, thus also atop the channel. (The dielectric under the gate is also commonly referred to as “gate oxide” or “gate dielectric”.) Gate 128 may be a portion of an elongate wordline (WL).
In modern CMOS technology, a shallow deep trench isolation (STI) is commonly used to isolate one (or more) transistors from other transistors, for both logic and memory. As shown in FIG. 1, a shallow deep trench 132 may be formed, surrounding access transistor 120 (only one side of the transistor is shown). Note that deep trench 132 extends over DT (node) poly 116, a top portion of which is adjacent the drain (D) of transistor 120. Therefore, deep trench 132 is less deep (thinner) over DT poly 116 and immediately adjacent the drain (D) of the transistor 120, and may be deeper (thicker) further from drain (D) of transistor 120 (and, as shown, over top portion of the DT poly 116 which is distal from (not immediately adjacent to) the drain (D) of the transistor 120). STI deep trench 132 may be filled with an insulating material, such as oxide (STI oxide) 134. Because of the thin/thick deep trench geometry which has been described, the STI oxide will exhibit a thin portion 134a where it is proximal (adjacent to) the drain (D) of the transistor 120, and a thicker portion 134b where it is distal from (not immediately adjacent to) the drain (D) of the transistor 120.
Although not shown, the deep trench (DT) may be “bottle-shaped”, such that it is wider in substrate 102 under BOX 104, and a thinner bottleneck portion of the deep trench extends through the BOX (and overlying SOI, not shown). The deep trench is typically filled with poly (DT Poly, compare 116), there is a lining of insulator (compare 114), and the deep trench is surrounded by the buried plate (compare 112). This forms the deep trench capacitor, which is generally not limited to SOI.
One form of deep trench capacitor is referred to as a metal-insulator-metal (MIM) due to the different types of layers used to form the capacitor. As described above, each metal layer creates a conductor or electrode either alone or in combination with surrounding structure. Each electrode is preferably sized to create as much capacitive capability as possible within each capacitor, i.e., the more surface area, the better the capacitive capabilities.
An outer or bottom electrode 140, which is approximately between insulator 110 and electrically joined with buried plate 112 may be formed in a number of ways. In one option, outer electrode 140 includes a deposited metal, e.g., tungsten, titanium, tantalum, ruthenium, cobalt, copper, aluminum, in the deep trench to couple to buried plate 112 of substrate 102. One challenge with using a deposited metal, however, is that residual oxides are created during the process that may degrade the overall capacitance at advanced technology nodes. That is, the residual oxide reduces the surface area of the outer electrode, diminishing its capabilities. The residual oxide may also degrade high frequency operation due to additional resistance from the oxide.
In order to address this situation, an alternative process may include forming a silicide, i.e., a silicon-metal conducting compound, in the deep trench. Unfortunately, current integrated circuit chip technology nodes (e.g., 22 nm and beyond) present a challenge in that a residual tensile stress is typically present after silicide formation due to the different coefficient of thermal expansion (CTE) between silicide and substrate 102. In smaller technology nodes, the impact of this residual tensile stress is magnified. The residual stress prevents successful formation of the silicide. Consequently, further scaling of integrated circuit chips may be hindered by the inability to scale the outer electrode of deep trench capacitors.